1. Field of the Invention
The present invention relates generally to signal processing circuits, and more particularly, to methods and circuits for processing input signals into square wave signals.
2. State of the Art
Circuits for processing input signals into square wave signals are known, such as Schmidt trigger circuits. However, Schmidt trigger circuits cannot provide the tight duty cycle control required for use as a system clock in circuits such as portable, battery powered telephone circuits and modems. In these applications, low amplitude sine wave signals on the order of 0.4 volts or lower are used to minimize electromagnetic radiation by eliminating sideband harmonics. Circuits such as portable telephones and modems also require a minimization of current consumption to preserve battery life.
A typical clock for use in battery powered circuits includes a local sine wave oscillator which outputs a sine wave of 13 megahertz (MHZ) and an amplitude of 0.4 volts to 1.2 volts. The sine wave is converted to a square wave that is then amplified to correspond with the supply voltage range of components in the circuit, such as a range of 3 volts where a low level voltage V.sub.SS is at circuit ground (i.e., 0 volts) and a high level voltage V.sub.DD is on the order of 3.0 volts. These circuits must also have the versatility of working with different frequency ranges, such as from DC to 20 MHZ to accommodate different circuit applications.
A clock circuit configured as a clock squarer amplifier 100 is shown in FIG. 1 as including two diode configured input transistors 102, 104 and two output transistors 106, 108 used to configure current mirrors. The transistors 102, 106 are illustrated as p-type transistors having their gates interconnected, having their sources connected to the source voltage V.sub.DD, and having their drains connected to drains of transistors 104, 108. The gates of n-type transistors 104, 108 are also interconnected, and the sources transistors 104, 108 are connected to the circuit ground, V.sub.SS. In the FIG. 1 circuit, the drains of transistors 102, 104 are interconnected via series connected resistors 110, 112 which "swamp out" the effective resistance of the diode configured input transistors 102, 104. The resistors 110, 112 are, for example, on the order of 10 kilo-ohms and together with a resistor 114 connected between an input 116 and an output 118, provide a resistive feedback circuit for establishing a bias point. This bias point sets the duty cycle of the output waveform (for example, at a duty cycle value of 50%).
As those skilled in the art will appreciate, the FIG. 1 circuit provides relatively good duty cycle regulation. However, this duty cycle regulation comes at the expense of high current consumption due to the poor drive ratio of the diode configured input transistors 102, 104.
During operation of the FIG. 1 circuit in a sine wave input mode (that is, where a sine wave is supplied to the input 116), current through the output transistors 106, 108 creates a crowbar current in the output stage from the source voltage V.sub.DD to the circuit ground V.sub.SS. This crowbar current in the output stage is a multiple of crowbar current which exists in the input stage due to incomplete shutoff of the transistors 102-108. The relatively high current in the output stage charges capacitances of the transistors included therein which must be overridden when switching the output stage transistors on or off, resulting in increased current consumption. In the sine wave input mode, the current consumption is amplitude dependent because the input stage operates as a voltage divider. The current consumption becomes especially high in a square wave input mode, not because of crowbar currents in the circuit, but because of large consumption within the input stage.
The physical size of the FIG. 1 circuit is of concern in the portable circuit applications mentioned previously, wherein packaging of the circuit as an integrated circuit is desirable. As such, current consumption cannot be reasonably decreased without an undesired increase in circuit size.
The relatively high current consumption of the FIG. 1 circuit can be traced to the large physical size of the diode configured input transistors 102, 104 and to the mirror transistors 106, 108. The transistors 106, 108 are typically eight times larger than the size of the input transistors 102, 104. Although inclusion of larger resistors 110, 112 would decrease current consumption at the input stage, the physical size of resistors 110, 112 is practically limited by size constraints when attempting to configure the circuit on a chip as an integrated circuit.
Those skilled in the art will appreciate that rather than increasing the size of the resistors 110, 112, decreased current consumption can also be achieved by increasing the channel length of transistors 102, 104 to thereby increase the voltage drop at these transistors. However, overall circuit size constraints renders such a solution impractical because any increased channel length of transistors 102, 104 requires a proportional increase in the channel length of transistors 106, 108. Because transistors 106, 108 are typically on the order of eight times larger than the transistors 102, 104, any such increase in the channel length of these transistors renders overall circuit size impractical. Given the size constraints imposed on the FIG. 1 circuit, a relatively high current consumption is deemed an acceptable tradeoff for the duty cycle control.
FIG. 2 shows another example of a clock circuit 200 configured as a differential stage clock squarer to achieve a relatively low current consumption at the expense of duty cycle control. The FIG. 2 circuit is configured with differential amplifiers 202, 204 which function as current sources, and output stage transistors 206, 208. Low current consumption is achieved in the FIG. 2 circuit as a result of using current sources to limit current. However, duty cycle control is compromised because of the difficulty in matching characteristics of the two differential amplifiers 202, 204. The FIG. 2 circuit also suffers from limited operating voltages which restrict versatility of the circuit. For example, the differential amplifiers 202, 204 include a configuration of cascoded transistors that inhibits the circuit from operating at low voltages.
Accordingly, it would be desirable to devise a clock circuit which possesses the advantages of low current consumption and tight duty cycle control, yet which remains versatile over relatively wide voltage and frequency ranges that include the low voltages desired for battery driven systems.